A sense amplifier is used for reading data in a DRAM. The sense amplifier functions to detect and amplify small differences in electric potential between a pair of bit lines.
FIG. 6 is a circuit diagram showing the basic configuration of a sense amplifier.
As shown in FIG. 6, a sense amplifier has a pair of P channel MOS transistors Tr1 and Tr2, and a pair of N channel MOS transistors Tr3 and Tr4. Specifically, Tr1 and Tr2 constitute a single set of pair transistors, and Tr3 and Tr4 constitute a single set of pair transistors. When the bit line BLT selected from the pair of bit lines BLT and BLB is at a high potential, the bit line BLT turns on transistor Tr4 and reduces the electric potential of the bit line BLB. The electric potential of the bit line BLT increases because the on electric current of the transistor Tr1 is thereby increased. An inverse operation is carried out when the electric potential relationship between BLT and BLB is inverted. The small difference in electric potential between the pair of bit lines BLT and BLB is amplified by the above operation.
The effect that the size of a sense amplifier has on the size of the entire chip is considerable because a sense amplifier is required for all bit line pairs. In other words, the sense amplifier is one circuit in particular that needs to be reduced in size. The sense amplifier functions to detect and amplify small differences in electric potential between bit lines. The small difference in electric potential corresponds to the electric charge held in a memory cell, and since this difference is very small, a balanced design in terms of resistance and capacitance in the pair of bit lines is required in order to correctly amplify the difference. If such a balance is not obtained, data may become inverted, and other critical DRAM failures may occur. Therefore, the balance between bit lines in the design of a sense amplifier must be given considerable attention.
A layout of pair transistors in a sense amplifier is disclosed in Japanese Laid-open Patent Application No. 2005-347578. The conventional layout of a sense amplifier disclosed in Japanese Laid-open Patent Application No. 2005-347578 is briefly described below.
FIG. 7 is a schematic plan view showing an example of the conventional layout of a sense amplifier.
As shown in FIG. 7, the sense amplifier 40 has a plurality of pair transistors PT composed of a combination of two transistors Tr in the active region 101, and these are disposed in correspondence with a plurality of bit lines arrayed with a uniform pitch. Specifically, the transistors Tr1 and Tr2 constitute a first pair transistor PT1, the transistors Tr3 and Tr4 constitute a second pair transistor PT2, the transistors Tr5 and Tr6 constitute a third pair transistor PT3,and the transistors Tr7 and Tr8 constitute a fourth pair transistor PT4. Such an active region 101 is provided for a P channel MOS transistor and an N channel MOS transistor, respectively (see FIG. 8 of Japanese Laid-open Patent Application No. 2005-347578).
However, progress in semiconductor technology continues to lead to smaller memory cells, and the spacing between bit lines determined by the size of the memory cell continues to narrow. For this reason, there is a need to reduce the pitch at which the pair transistors are disposed in a corresponding manner. However, with a conventional sense amplifier layout, it is becoming difficult to reduce the configurational pitch of the pair transistors in correspondence with the narrowed pitch of the bit lines. This is because a gate, an impurity diffusion layer that forms a source and drain, contacts that supply electric potential to the source and drain, and other components are required to form a transistor. In other words, the direction in which the pair transistors are arrayed (the lateral direction in the diagram) is determined by the gate, source, and drain of the pair transistors, and the size and spacing required for the configuration to function as an element are approaching their limits. Conversely, when the spacing is narrowed further to surpass these limits in terms of design, short-circuiting may occur at unintended contact points, wiring may be similarly broken if the width and size is reduced, and contacts may be interrupted.
FIG. 8 is a schematic plan view showing another example of the layout of a conventional sense amplifier.
As shown in FIG. 8, the sense amplifier 50 is the same circuit as in FIG. 7, and has four sets of pair transistors composed of transistors Tr1 to Tr8. Each set of transistors Tr1 and Tr2, Tr3 and Tr4, Tr5 and Tr6, and Tr7 and Tr8 constitutes a pair transistor, and each pair of bit lines BL1T and BL1B, bit lines BL2T and BL2B, and so forth constitutes a corresponding pair of bit lines. Among the four sets of pair transistors composed of transistors Tr1 to Tr8, the transistors Tr1, Tr2, Tr5, and Tr6 are disposed in an active region 101A of the first column, and the transistors Tr3, Tr4, Tr7, and Tr8 are disposed in an active region 101B of the second column. The position in the lateral direction of the transistors disposed in the active region 101A of the first column and the position in the lateral direction of the transistors disposed in the active region 101B of the second column are offset by a half pitch. The previously physically limited transverse wiring width, spacing, and other properties are provided with a greater degree of freedom, and a pair transistor in which the pitch of the bit lines has been reduced can be obtained (see FIG. 9 of Japanese Laid-open Patent Application No. 2005-347578).
However, in the conventional pair transistor layout shown in FIG. 8, the size in the lateral direction (row direction) is determined by the bit lines, but since the pair transistors are stacked two deep in the column direction, the size in the perpendicular direction of the pair transistors is increased.